microprocessor

  8279 Block Diagram CPU interface and control section Scan section 8279 Keyboard section Display section 1 .CPU Interface and Control Section Data Buffers The data buffers are 8-bit bi-directional buffers that connect the internal data bus to the external data bus. I/O Control The I/O control section uses the A 0 , CS, RD and WR signals to control data flow to and from the various internal registers and buffers. he data flow to and from the Block Diagram of 8279 is enabled only when CS = 0; otherwise the 8279 signals are in a high impedance state. Control and Timing Registers The control and timing registers store the keyboard and display modes and other operating conditions programmed by the CPU. 2. Scan Section (Scan counter) The scan section has a scan counter which has two modes :  Encoded mode decoded mode. Encoded Mode In the encoded mode, the scan counter provides a binary count from 0000 to 1111 on the four scan lines (SC 3  — SC 0 ) with active high outputs....

  Interrupt Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt Types of Interrupts Hardware interrupt it is caused by any peripheral device by sending a signal through a specified pin to the microprocessor. The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority.  Maskable Interrupt  An Interrupt that can be disabled or ignored by the instructions of CPU are called as Maskable Interrupt  Eg: ► INTR  Non-Maskable Interrupt  An interrupt that cannot be disabled or ignored by the instructions of   CPU are called as Non-Maskable Interrupt. A Non-maskable interrupt is often used when  response time is...